Liquid crystal display devices (LCDs) characterized by their thin design, light weight and low power consumption have come into widespread use in recent years and are utilized in the display units of mobile devices such as portable telephones (mobile telephones or cellular telephones), PDAs (Personal Digital Assistants) and laptop personal computers. A system for driving these liquid crystal display devices is classified into a simple matrix type and an active matrix type. It is the active matrix type that is suitable for achieving higher definition. The active matrix type display device has a switching device for each pixel.
Since the active matrix type display system has a thin film transistor (Thin Film Transistor: hereinafter abbreviated as a “TFT”) as the switching device for controlling an individual pixel, image display with high quality is possible, thus being suited to achieving the higher definition. A configuration of a conventional active matrix type liquid crystal display device and a driving method of the conventional active matrix type liquid crystal display device will be shown below.
FIG. 14 is a diagram showing an example of a typical configuration of the conventional active matrix type liquid crystal display device. Referring to FIG. 14, this active matrix type liquid crystal display device includes a liquid crystal panel 101, a scan driver, a column driver 109, and a display controller 120. The liquid crystal panel 101 has two substrates and a liquid crystal sandwiched between these two substrates. On one substrate, a plurality of data lines 102 are arranged in a vertical direction of the drawing, a plurality of scan lines 103 are respectively arranged in a horizontal direction of the drawing, and pixel circuits 104 are laid out at intersections between the data lines 102 and the scan lines 103 laid in the form of a matrix. On the other substrate, a common electrode 110 is provided for the entire surface of the other substrate, and a predetermined voltage is given to this common electrode 110.
The pixel circuit 104 shown in FIG. 14 corresponds to a circuit equivalent to one liquid crystal display element. The pixel circuit 104 includes a TFT 105, a pixel electrode 117, a liquid crystal capacitance 106, and a storage capacitance 107. The TFT 105 is connected between a data line 102 and the pixel electrode 117, and a control terminal thereof is connected to a scan line 103. The liquid crystal capacitance 106 and the storage capacitance 107 are connected between the pixel electrode 117 and the common electrode 110. When the TFT 105 is turned on according to a scan signal on the scan line 103, a gray scale signal on the data line 102 is supplied to the pixel electrode 117. When the TFT 105 is turned off, the gray scale signal is held by the liquid crystal capacitance 106 and the storage capacitance 107. Since the transmittance of the liquid crystal changes according to a potential difference between the pixel electrode 117 and the common electrode 110, gray scale display of the liquid crystal can be performed by supplying the voltage of the gray scale signal to the pixel electrode.
FIG. 15 is a diagram showing an example of a typical configuration of the conventional column driver 109 used in the device shown in FIG. 14. Referring to FIG. 15, the column driver 109 includes a shift register 208, a data register 207, a data latch 206, a level shifter 205, a gray scale voltage generation circuit 204, digital-to-analog converter circuits 202, and buffer amplifiers 201. The buffer amplifiers 201 include voltage-follower type operational amplifiers 112.
An operation of the column driver 109 shown in FIG. 15 will be described. The shift register 208 outputs a shift pulse according to a clock signal CLK. The data register 207 sequentially shifts up input video data responsive to the shift pulse output from the shift register 208 and distributes the video data according to the number of outputs of shift pulses. The data latch 206 temporarily holds the video data distributed from the data register 207, and outputs to the level shifter 205 entire outputs thereof in unison responsive to a timing of a control signal STB.
The level shifter 205 converts the voltage amplitude of the video data to the voltage amplitude corresponding to a liquid crystal driving voltage, for output to the digital-to-analog converter circuits (D/A converter circuits) 202.
The D/A converter circuits 202 receive a plurality of gray scale voltages output from the gray scale voltage generation circuit 204, select gray scale voltages based on the video data, and output the gray scale voltages as gray scale signals.
The buffer amplifier 201 includes the operational amplifiers 112 corresponding to the number of the outputs thereof. The buffer amplifier 201 receives the gray scale signals output from the D/A converter circuits 202, and output to output terminals 810 the gray scale signals that have been current amplified. The output terminals 810 of the column driver 109 (See FIG. 14) are connected to corresponding one ends of the data lines 102.
Next, a method of driving the conventional active matrix type liquid crystal display device shown in FIG. 14 will be described. FIG. 16 is a diagram showing a timing chart of typical signals for driving the conventional active matrix type liquid crystal display device described with reference to FIGS. 14 and 15. Referring to FIGS. 14 and 15 and timing waveforms in FIG. 16, the method of driving the conventional active matrix type liquid crystal display device will be described below.
FIG. 16 shows a control signal STB, video data DATA (x−1), DATA (x), and DATA (x+1) associated with one data line, scan signals Y (x−1), Y (x), and Y (x+1), and a driving voltage waveform for the one data line.
The video data DATA (x) and DATA (x+1) show data signals output from the data latch 206 (refer to FIG. 15), and are output to the level shifter 205 (refer to FIG. 15) responsive to rise timings T1 and T2 of the control signal STB.
Accordingly, gray scale signals corresponding to the video data DATA (x), DATA (x+1) are also output from an operational amplifier 112 (refer to FIG. 15) at substantially the same times as the timings T1 and T2, thereby driving the data line.
On the other hand, the scan signals Y (x) and Y (x+1) show the scan signals on the adjacent scan lines. The scan signal Y (x) is kept HIGH from the timing T1 to the T2 and kept LOW otherwise. The scan signal Y (x) is driven from the timing T1 to T2. Then, the TFTs for one row connected to the scan line are turned on, and the gray scale signal output to each of the data lines is supplied to each pixel electrode of the pixel circuits for the one row.
The scan signal Y (x+1) is kept HIGH from the timing T2 to a timing T3 and kept LOW otherwise. From the timing T2 to the timing T3, the gray scale signal output to each of the data lines is supplied to each pixel electrode of the pixel circuits for the next row.
As a data line driving voltage, the gray scale signal corresponding to the video data DATA (x) and the gray scale signal corresponding to the video data DATA (x+1) are driven during a period from the timing Ti to the T2 and from a period the timing T2 to the timing T3, respectively, and are supplied to the pixel electrodes of the pixel circuits that are adjacent to each other in the vertical direction in response to the scan signals Y (x) and Y (x+1).
The data line driving voltage in FIG. 16 is in the form of the gray scale signal with a negative polarity (−) during the period from the timing T1 to the timing T2. Then, during the period from the timing T2 to the timing T3, the data line driving voltage is in the form of the gray scale signal with a positive polarity (+). The polarity of the gray scale signal is defined with reference to a voltage VCOM of the common electrode 110.
When the polarity is changed as described above, a polarity inversion is performed for each pixel row. This is a common method of enhancing display quality of the liquid crystal panel.
Further, assume that it is set so that the polarities of the gray scale signals output to the adjacent data lines at the same timing become different, though the setting is not shown in FIG. 16. Then, a polarity change is performed for each pixel column. This is also the common method of enhancing the display quality of the liquid crystal panel.
Further, supply and holding of the gray scale signal to each pixel electrode is repeated for each frame period, and every time the supply and holding is performed, the polarity of the gray scale signal is reversed. This is a common liquid crystal driving method of preventing liquid crystal deterioration.
The foregoing description was given about driving of one data line associated with the video data DATA (x) or DATA (x+1) and supply of the gray scale signal to the pixel electrodes, by referring to FIG. 16. The same holds true for other data lines.
Next, the data line driving voltage supplied to each of the pixel circuits 104 in the display panel 101 in FIG. 14 will be described in detail.
FIG. 17 is a diagram showing an equivalent circuit 113 for one data line 102 and one pixel circuit 104. Incidentally, in the equivalent circuit 113 for the data line in FIG. 17, one end of the data line to which an output terminal 810 of the column driver is connected is indicated by a terminal NN1 (referred to as a “data line near end”) and the other end of the data line is indicated by a terminal FF1 (referred to as a “data line far end”).
Generally, an equivalent circuit for wiring can be represented by a configuration in which a resistance element and a capacitance element are connected in a plurality of stages, as shown in FIG. 17. Each resistance element is determined by the material of the wiring, the length of the wiring, and the sectional area of the wiring that constitute the data line. Each capacitance element is determined by a configuration of each pixel circuit such as the capacitance of the liquid crystal between the data line and the common electrode 110 and the capacitance at the intersection between the data line with a corresponding scan line.
Accordingly, as a screen of the display panel 101 becomes larger, and as a resolution of the display panel 101 becomes higher, an impedance of the data line is increased. On the other hand, only the one pixel circuit 104 connected to the data line far end FF1 is shown, and other pixel circuit is omitted. The configuration of the pixel circuit 104 is as described by referring to FIG. 14.
FIG. 13 shows voltage waveforms WA, WB, and WC of the data line near end NN1, the data line far end FF1, and the pixel electrode 117 in FIG. 17, respectively. Each of the voltage waveforms WA, WB, and WC shows a change before and after the timing T2 of the timing chart in FIG. 16 (which means that Tr=T2 in FIG. 13).
Referring to FIG. 13, the voltage waveform WA (voltage waveform at the data line near end NN1 in FIG. 17) undergoes a voltage change at a constant slew rate after the timing T2, and reaches a target gray scale signal voltage after a timing TA. This slew rate is determined by driving capability of the operational amplifier 112 in FIG. 15.
After the timing T2, the voltage waveform WB (voltage waveform at the data line far end FF1) gently changes, and reaches the target gray scale signal voltage after a timing TB.
The change of the voltage waveform WB at this point is determined by a rate of relaxation within the data line in which electric charges supplied to the data line near end NN1 depend on the impedance of the data line. That is, the voltage waveform WB is determined by the voltage waveform WA and the impedance of the data line.
The voltage waveform WC (voltage waveform at the pixel electrode 117) changes more slowly than the voltage waveform WB after the timing T2, and reaches the target gray scale signal voltage after a time TC. The change of the voltage waveform WC depends on the voltage waveform WB and the mobility of an electric charge in the TFT 105 because the voltage waveform WB is transmitted through the TFT 105.
Currently, in the common liquid crystal display device, the TFT 105 of the liquid crystal panel 101 is formed of amorphous silicon. Since the mobility of an electric charge of the amorphous silicon TFT is comparatively low, the voltage waveform WC becomes a waveform with a delay further larger than that of the voltage waveform WB.
Accordingly, a period 1H for driving the gray scale signal corresponding to one video data (corresponding to an interval between the timing T1 and the timing T2, and between the timing T2 and the timing T3 in FIG. 16) in the timing chart of FIG. 16 is set based on the time TC (rise delay time of a pixel electrode, see FIG. 13).
In order to reduce the time TC, it is required that the liquid crystal panel 101 should be so configured that the impedances of the data line 102 and the TFT 105 become low or that the driving capability of the operational amplifier 112 should be enhanced in the column driver and the slew rate of the voltage waveform WA should be increased.
A method of reducing a rise time of the data line driving voltage without increasing the current driving capability of the operational amplifier is described in Patent Document 1 (Japanese Patent Kokai Publication No. JP-P2001-22328A), for example. In Patent Document 1, in order to reduce the impedances, two measures are taken after a configuration shown in FIG. 18 has been made. That is, within a precharging period,    1) connection that reduces a delay time of a decoder output (time for stabilizing the output of a decoder circuit) is performed, and    2) a predetermined potential is set for the data line in advance by precharging.
Decoder circuits 278 and 279, are disconnected from amplifier circuits 271 and 272 within the precharging period. Transfer gate circuits TG31 and TG32 in an off state are connected to outputs of the decoder circuits. Since input impedances of the transfer gate circuits TG31 and TG32 are far smaller than those of the amplifier circuits 271 and 272, delay times of the outputs of the decoder circuits can be reduced. At the same time, by supplying precharge voltages (VHpre, VLpre) to inputs of the amplifier circuits 271 and 272, respectively, drain lines are precharged. A higher-speed operation is thereby achieved.
In such a configuration, enhancing the current driving capability of the operational amplifier becomes unneeded. However, compared with the configuration of the conventional display device, a precharge control circuit constituted from the transfer gate circuits TG31 to TG34 is newly required. Supply of a predetermined voltage by precharging thereby becomes necessary.
Further, in this configuration, charging and discharging times required for obtaining a voltage from the precharging potential to a target gray scale voltage becomes necessary.
As another method of reducing the rise time of the data line driving voltage, a method of raising a video signal within a portion of a reset period is described in Patent Document 2 (Japanese Patent Kokai Publication No. JP-P2004-61970A), for example. Referring to Patent Document 4, an organic EL (Electro Luminescence) display device is taken as an example, and control is performed according to a timing chart as shown in FIG. 19. An organic EL display element emits light according to an amount of a supplied current. Thus, variation in the amount of the supplied current that depends on a TFT degrades display quality. For this reason, it is usually a common practice to provide the reset period within a horizontal blanking period (period from the end of supplying a video signal by sweeping a line to the start of sweeping a next line), which is a start period of a horizontal period, and apply a correction signal to pixels.
However, due to the higher definition, the horizontal period is reduced, and the horizontal blanking period is also reduced. Thus, it becomes difficult to perform resetting in this period.
Then, by providing the reset period that is overlapped with a horizontal scan period (period from supply of a video signal voltage to a data line from wiring for supplying a video signal), and causing the video signal on the wiring for supplying the video signal to reach a set potential in advance in a period in which the wiring for supplying the video signal and the data line are disconnected, the rise time of the data line driving voltage after completion of the reset period can be reduced.
However, the above described configuration is the method of securing the reset period, and does not solve shortage of a time for supplying the voltage to the pixel electrodes. It is because the time for supplying the voltage to the pixels in the configuration described before is the time obtained by subtracting from the horizontal period the horizontal blanking period and a portion of the horizontal scan period (period overlapped with the reset period).
The two Patent Documents described above are examples in which the configuration of a data line driver circuit in the display device and a control method of the data line driver circuit have been changed.
In addition to the above documents, Patent Documents and Non-patent Documents that will be described below are referred to as literatures related to the invention disclosed in the specification of the present application. Incidentally, in addition to the Patent Document 1, Patent Document 6, Patent Document 10, and Patent Document 11 disclose a configuration in which a switch is provided between an amplifier for data line driving and a data line.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2001-22328A
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2004-61970A
[Patent Document 3]
Japanese Patent Kokai Publication No. JP-A-58-099033
[Patent Document 4]
Japanese Patent Kokai Publication No. JP-A-58-121831
[Patent Document 5]
Japanese Patent Kokai Publication No. JP-A-61-214815
[Patent Document 6]
Japanese Patent Kokai Publication No. JP-A-11-095729
[Patent Document 7]
Japanese Patent Kokai Publication No. JP-A-11-249624
[Patent Document 8]
Japanese Patent Kokai Publication No. JP-A-6-326529
[Patent Document 9]
Japanese Patent Kokai Publication No. JP-A-9-244590
[Patent Document 10]
Japanese Patent Kokai Publication No. JP-P2003-162263A
[Patent Document 11]
Japanese Patent Kokai Publication No. JP-P2004-318170A
[Non-patent Document 11]
Technical Report, CAS83-82, p. 7, “CMOS Switched-Capacitor Operational Amplifier with Auto-zero Offset Compensation”, 1983